1. Field of the Invention
The present invention relates to the distribution of signals in high-speed digital circuitry, particularly where the variation in the propagation delay to various parts of the circuitry is relatively large in relation to timing constraints imposed on the operation of the circuitry by, for example, a fast system clock.
2. Description of the Related Art
FIG. 1 of the accompanying drawings shows a printed circuit board (PCB) 1 carrying a source chip 2 and a destination chip 3. Signal producing circuitry 4 on the source chip 2 generates n individual channels of data D0 to Dn−1 which are communicated respectively to n signal processing circuitry portions 50 to 5n−1 on the destination chip 3 via n respective output pins 60 to 6n−1 of the source chip 2, n respective connection lines 80 to 8n−1 connecting the source chip 2 with the destination chip 3 and n respective input pins 70 to 7n−1 of the destination chip 3. Each of the data channels D0 to Dn−1 is a serial stream of 1-bit data which is synchronised in the source chip 2 with a clock signal CK generated within the signal producing circuitry 4.
In the FIG. 1 example, the distance “a” separating the source chip 2 and the destination chip 3 is relatively small, for example of the order of 2 to 3 cm, making it feasible to operate a synchronous interface between the two chips. With a synchronous interface, each of the serial data channels D0 to D−1 is synchronised on the source chip 2 with the clock signal CK generated on the source chip 2, and the clock signal CK is itself communicated from the source chip 2 to the destination chip 3 via an output pin 6CK on the source chip 2, a connection line 8CK and an input pin 7CK on the destination chip 3. Since the separation “a” between the source chip 2 and the destination chip 3 is relatively small, the relative timings of the signals communicated between the chips are not influenced too greatly by variations in interconnect loading and therefore the data channels D0 to Dn−1 can be expected to exhibit a reasonable degree of synchronicity with the clock signal CK upon their arrival at the input pins 7 of the destination chip 3. Were an asynchronous interface to be used instead, where the clock signal CK is not communicated from the source chip 2 to the destination chip 3, n separate clock recovery circuits would be required on the destination chip 3 in order to recover n respective individual clocks from the n separate data channels D0 to Dn−1, with consequent problems relating to the realignment of the data channels.
The clock signal CK which is received at the input pin 7CK of the destination chip 3 is distributed to each of the signal processing circuitry portions 50 to 5n−1 for use in controlling the timing of operations by those circuitry portions.
A reset signal R is also produced by the signal producing circuitry 4 of the source chip 2 which is used to reset each of the circuitry portions 5. This reset signal R is also communicated from the source chip 2 to the designation chip 3 via an output pin 6R of the source chip 2, a connection line 8R and an input pin 7R of the destination chip 3. From the input pin 7R the reset signal R is distributed to each of the signal processing circuitry portions 50 to 5n−1.
The input pins 70 to 7n−1 are separated from each other by a distance “b”. Circuitry layout and signal distribution considerations dictate that each of the n signal processing circuitry portions 50 to 5n−1 is advantageously positioned as close as possible to its corresponding input pin 7, with the n signal processing circuitry portions 50 to 5n−1 being laid out in a line substantially parallel with the line of input pins 70 to 7n−1 and with each of the signal processing circuitry portions 50 to 5n−1 being opposite its corresponding input pin 7. Therefore the distance “c” separating the signal processing circuitry portions 5 from one another is advantageously substantially the same as the pin separation “b”. The distance between the first signal processing circuitry portion 50 and the last signal processing circuitry portion 5n−1 is “d”, or approximately (n−1)*c.
In a typical application, the pin separation “b”, and therefore also the separation “c” between adjacent signal processing circuitry portions 5, is of the order of 0.5 mm. With sixteen channels of data D0 to D15, and sixteen corresponding signal processing circuitry portions 50 to 515, the overall separation “d” between the first and final signal processing circuitry portions 50 and 515 is of the order of 8 mm. The overall dimensions of such a destination chip 3 would be of the order of 10 mm by 10 mm.
With a destination chip 3 having such dimensions, the capacitive and resistive loading of the interconnect wiring between the input pins 7 and the signal processing circuitry portions 5 is highly significant, and even at moderate clock frequencies this leads to relatively large and highly variable signal transition times (i.e. unpredictable signal propagation delays). Consequently, some sort of signal distribution and buffering network is required to control the propagation of signals from the input pins 7 to the signal processing circuitry portions 5 in the destination chip 3.
FIG. 2(A) of the accompanying drawings shows a simple example of a clock distribution tree which can be used in the destination chip 3 of FIG. 1 to route the received clock signal CK from the clock input pin 7CK to each of four signal processing circuitry portions 50 to 53. In the example shown in FIG. 2(A), only four signal processing circuitry portions 50 to 53 are shown for ease of illustration. The clock distribution circuitry 9 of FIG. 2(A) comprises ten buffers 100 to 109 arranged in a tree-like formation with a single buffer 100 at the root of the tree and four buffers 103, 106, 108 and 109 at the ends of the tree branches. The received clock signal CK branches into four separate clock signals CK0 to CK3 which are input to respective signal processing circuitry portions 50 to 53.
FIG. 2(B) of the accompanying drawings shows similar distribution circuitry 11 for distribution of the received reset signal R. The reset signal distribution circuitry 11 also comprises ten buffers 120 to 129 arranged in a similar configuration to the ten buffers 100 to 109 of FIG. 2(A).
Each of the signals CK0/R0 to CK3/R3 in FIGS. 2(A)/2(B) propagates through a different set of four buffers. For example, clock signal CK1 arrives at its destination having travelled through buffers 100, 104, 107 and 108. Each signal therefore passes through the same number of buffers to arrive at its destination. The wiring portions are not all of the same length, which leads to some small differences in propagation time amongst the signals CK0 to CK3 and amongst the signals R0 to R3. However, provided that the wiring propagation times are small in comparison with the switching times of the buffers, the signals CK0 to CK3 and R0 to R3 arrive at the signal processing circuitry portions without significant timing differences.
In practice a more efficient distribution tree having fewer buffering stages than those illustrated in FIGS. 2(A) and 2(B) would be used. However, even with signal distribution arrangements where measures have been taken to equalise the path lengths and propagation delays of each of the signals CK0 to CK3 or R0 to R3, there can be substantial differences, i.e. skew, in the arrival times of different clock signals CK and different reset signals R at the signal processing circuitry portions 5. This is because the path taken through the distribution network by one of the signals CK0 to CK3 in FIG. 2(A) or R0 to R3 in FIG. 2(B) is different to the path taken by another such signal, with each signal travelling through a different set of buffers. As a consequence, the overall delay of each distributed signal will be different. Furthermore, even when a single signal is considered, there can be substantial variation, i.e. jitter, in its arrival time at its particular intended signal processing circuitry portion 5. There are several reasons for such skew and jitter.
Firstly, manufacturing or process variations will result in variations between the size or strength of the individual buffers, their switch times, and their loading effects. Such process variations will tend to be small across a single chip but can be much larger from one chip to another. Secondly, there will be random or systematic variations in supply voltage applied to each of the individual buffers, for example up to ±5%. Thirdly, there will be variation in the operating temperature at different parts of the circuitry and from device to device. Such temperature variations will tend to be small across a single chip at any one time but the circuitry may be required to operate over a wide range of operating temperatures, for example from −40° C. to +125° C. These uncertainties in operating conditions are referred to generally as “process-voltage-temperature” variations, or PVT variations.
PVT variation within a single device results in timing skew or jitter being manifested in the signals at the end of a distribution network such as that of FIG. 2(A) or FIG. 2(B), which can typically be of the order of 15% of the overall distribution delay which is experienced by a signal through the distribution network, even between adjacent distributed signals. Electrical (voltage) variations tend to dominate this “local” PVT variation since temperature and process variations tend to be small across a single device at any one time. For example, a fluctuating supply voltage may lead to fluctuating signal rise and fall times, which will result in jitter.
“Global” PVT variations, which are PVT variations from one device to another or from one time to another in a single device, also have significant timing implications. For example the propagation time of a particular signal in a device will change markedly as the operating temperature of the device varies between, for example, −40° C. and +125° C., and process variations between devices will also have a significant effect.
In the context of clocked circuitry such as that shown in FIG. 1, these local and global PVT variations can be large enough to make it impossible to guarantee that a signal will arrive at its destination in a predetermined clock cycle, for example. This problem becomes particularly serious where the frequency of the clock signal is very high, bordering on the maximum speed of operation of the circuit elements making up the circuitry, for example of the order of 600 or 700 MHz for a 0.18 μm CMOS process.
FIGS. 3(A) to 3(C) illustrate these effects of local and global PVT variation on the timing characteristic of a distributed clock signal. FIG. 3(A) shows the received clock signal CK at the clock input pin 7CK. The clock signal has a clock cycle period of T. The delay effects will be illustrated with reference to the rising edge E of the clock signal CK of FIG. 3(A). All timing values are measured with respect to the 50% amplitude threshold of a rising edge.
FIG. 3(B) illustrates the delay of a distributed clock signal (for example CK3 of FIG. 2(A)) with PVT conditions at one extreme of the global PVT variation range for a particular set of tolerances. The minimum delay time Tf in the rising edge under these conditions is illustrated by the solid-line rising edge f of FIG. 3(B). Local PVT variations as explained above will also cause a timing jitter Jf of approximately 15% of the overall minimum PVT delay Tf, so that while a clock signal distributed to one part of the circuitry (for example CK3 of FIG. 2(A)) may be delayed by a time Tf, another clock signal distributed to a different part of the circuitry (for example CK0 of FIG. 2(A)) may be delayed by a different time Tf* with respect to the rising edge E. The maximum delay time for the same set of extreme global PVT conditions is illustrated by the dashed-line rising edge f* in FIG. 3(B).
FIG. 3(C) shows the delay experienced by the rising edge of clock signal CK with PVT conditions at the other extreme of the global PVT tolerance range, that is to say the maximum global PVT delay. The maximum delay experienced by the rising edge E under these conditions is Ts, as illustrated by the solid-line rising edge s of FIG. 3(C). Local PVT variation causes jitter Js between different clock signals of approximately 15% of Ts, so that for clock signals distributed to different parts of the circuitry the rising edge delay time could be any time between Ts* and Ts when the PVT conditions are at this end of the PVT tolerance range.
Referring to the timing symbols of FIGS. 3(A) to 3(C), in one practical example of clock distribution circuitry the clock signal CK has a frequency of 673 MHz, so that the clock cycle period T is 1.48 ns. The minimum clock delay Tf is 720 ps, so that Tf* (=Tf+15%) is 830 ps. The clock distribution jitter Jf in these circumstances is then 110 ps. The rising edge time is of the order of 180 ps. The maximum clock delay Ts in this example is 1830 ps, so that Ts* (=Ts−15%) is 1555 ps. The clock distribution jitter Js in these circumstances is then 275 ps. The rising edge speed is of the order of 280 ps.
It can be seen from the above illustration with reference to FIGS. 3(A) to 3(C) that the clock distribution delay can actually be longer than the clock cycle period T, with the time overshoot Tp of FIG. 3(C) varying from 75 ps to 350 ps under “maximum delay” PVT conditions. The clock distribution delay can also be as low as 720 ps, which is less than half a clock cycle period, under “minimum delay” PVT conditions.
Since the reset signal R is also distributed in a similar way to the clock signal CK (see FIGS. 2(A) and 2(B)), the reset signal R also exhibits wide variation in propagation delay. The adverse consequences of these variations in propagation delay across PVT will now be illustrated with reference to FIGS. 4(A) to 4(C) of the accompanying drawings.
FIG. 4(A) shows the clock signal CK and the reset signal R which are received at the input pins 7CK and 7R respectively of the destination chip 3 of FIG. 1. The first clock cycle CYCLE 1 commences with the rising edge E of the clock signal CK. Suppose that the clock signal CK and reset signal R are intended to be used as the clock and reset inputs respectively of a register. The reset signal must be present and stable a minimum set-up time ts before the rising edge of the clock signal CK.
FIG. 4(B) shows the clock signal CKA and reset signal RA which are received at one of the signal processing circuitry portions 5 of FIG. 1 after distribution through circuitry such as that shown in FIGS. 2(A) and 2(B). In the FIG. 4(B) example, the clock signal CKA is delayed by a time dCKA with respect to the original clock signal CK. The reset signal RA is delayed by a time dRA with respect to the original reset signal R. In the FIG. 4(B) example, the clock delay dCKA and reset delay dRA are approximately the same, with the result that the rising edge in RA occurs more than the set-up time ts before the rising clock edge A of the clock signal CKA in CYCLE 1 of FIG. 5(B). Thus, as intended the reset signal given in CYCLE 1 of FIG. 5(A) causes the register to be reset at the rising edge A.
FIG. 4(C) illustrates the clock signal CKB and reset RB which are received at a different one of the signal processing circuitry portions 5 of FIG. 1 within the same destination chip 3. The clock signal CKB is delayed by a time dCKB with respect to the original clock signal CK, and the reset signal RB is delayed by a time dRB with respect to the original reset signal R. In the FIG. 4(C) example, the clock delay dCKB is approximately equivalent to the delay dCKA experienced by clock signal CKA of FIG. 4(B), but due to PVT variations the delay dRB experienced by the reset signal RB is greater than the delay dRA experienced by the reset signal RA of FIG. 4(B). In the FIG. 4(C) example, the reset signal RB has been delayed to such an extent that it would no longer meet the set-up time ts of the register in CYCLE 1 of FIG. 4(C). Thus the register would not be reset until the rising edge B.
It is apparent from FIGS. 4(B) and 4(C) that due to PVT variations the clock cycle in which the reset signal reaches its destination can vary. This variation can occur even where there is no clock variation or jitter at all, the variation in the clock cycle timing of arrival arising entirely from the variation in the propagation time of the reset signal itself. The variation is of course exacerbated when clock timing variations, which inevitably also occur in practice, are taken into account. This is true even though the clock and reset distribution trees of FIGS. 2(A) and 2(B) are matched such that the delay of each distributed clock signal CK0 to CKn−1 nominally matches the delay of its corresponding distributed reset signal R0 to Rn−1. In practice, the matching of delays is only precisely possible for a particular set of PVT conditions, and cannot always be achieved across the entire range of PVT conditions. Therefore circuitry which may be operating correctly at one particular point in the PVT range may not operate correctly at a later time when, for example, the temperature has drifted higher over that period of time.
This timing problem can also arise even if the reset signal R is synchronised to one of the rising edges of the clock signals CK, for example by synchronising circuitry connected with the clock and reset input pins 7CK and 7R in FIG. 1. In this case, as shown in FIG. 5(A) of the accompanying drawings the rising edge of the reset signal R is synchronised with the rising edge E of the clock signal CK in CYCLE 1. FIG. 5(B) of the accompanying drawings shows the situation where the clock signal CKA is delayed with respect to the original clock signal CK by a relatively large time dCKA, which is larger than the overall clock cycle period. On the other hand, the reset signal RA is delayed by a shorter time dRA with respect to the original reset signal R, the difference between dRA and dCKA arising from PVT variations. As a result the reset signal is received at the register at a time which meets the set-up requirements of the register in CYCLE 0 of FIG. 5(B), which is the cycle preceding the CYCLE 1 in which the reset signal was given in FIG. 5(A). Thus the register would be reset on rising edge B rather than rising edge A of the clock signal CKA, as intended.
Although FIGS. 1 to 5 have illustrated the problems of distribution of a signal from a source node of a chip to a plurality of destination nodes on a chip the same problem will also arise even when a reset signal (or other such signal) is being distributed from a source node to a single destination node. For example, although FIGS. 4(B) and 4(C) were described above as showing the timing of a clock signal CK and reset signal R distributed from a single node point to two different destination nodes A and B within the same circuitry, those figures could also represent the timing of signals distributed from a source node to a single destination point at two different times A and B for the same device, or between equivalent source and destination nodes in two different devices A and B.
The problem will arise in any device in which variation in a minimum propagation time of a transmission signal, such as a reset signal as described above, from a source node to a destination node is sufficiently large, relative to a clock period at an intended clock frequency of the device, to cause variation in a clock cycle in which the transmission signal reaches the destination node. In practice, a transmission path between the source and destination nodes having the minimum propagation time may be exclusively passive (wiring portions or tracking), or may include active elements such as gates or buffers. The minimum propagation time relates to the fastest practically-realisable such transmission path for a particular device.